Project Overview

Matrix-vector multiplication (MVM) is one of the most common operations in machine learning applications. Performing MVM requires many multiply and accumulate operations, which takes a lot of time and energy in a typical CPU. Moving the required data back and forth in between the CPU and memory consumes a lot of energy in a traditional system. Compute-in-memory (CIM) technologies pose a potential solution to speeding up these processes by eliminating the memory bottleneck and allowing for parallel computation. ReRAM is an emerging, low-power, and non-volatile memory technology which may be used for CIM. Using ReRAM for CIM may require a rethink of ReRAM architectures. First, there is significant potential for impact from noise, both from the internal architecture of the ReRAM matrix as well as device noise from other chip components. Second, there are limited opportunities for ReRAM chip fabrication. For these reasons, we will design a fabricated test vehicle for ReRAM architecture exploration and characterization. The test vehicle will include multiple distinct ReRAM implementations in one design, resulting in a final chip that can test multiple implementations for research purposes. Ultimately, the test vehicle will be fabricated using the Skywater 130nm process and Efabless tools to give ourselves the best chance of getting a physical tape out.